SH7720 Datasheet, PDF (72/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview
1.2 Block Diagram
Super H
CPU core
DSP core
User break
controller (UBC)
X bus
Y bus
X/Y memory
Instruction/data for
CPU/DSP (16 kbytes)
Cache access
controller (CCN)
Internal bus
Cache
memory
(32 kbytes)
CPU bus
Memory
management
unit (MMU)
Internal bus
External bus
Bus state
controller
(BSC)
Peripheral
bus controller
Peripheral bus
Direct memory
access controller
(DMAC)
SSL
accelerator
(SSL)
USB host
controller
(USBH)
512-byte
RAM
LDC
controller
(LCDC)
2.56-kbyte
line buffer
User debugging
interface (H-UDI)
Interrupt
controller
(INTC)
Realtime
clock
(RTC)
Clock pulse
generator
(CPG)
Timer unit
(TMU)
Peripheral bus
Serial communication
interface 0 with FIFO
128-byte FIFO
(SCIF0/IrDA)
Serial communication
interface 1 with FIFO
128-byte FIFO (SCIF1)
I²C ^576-byte
SRAM
Analog front end
interface (AFEIF)
USB function controller
1-kbyte FIFO (USBF)
Compare
match
timer (CMT)
16-bit
A/D
D/A
timer pulse converter converter
unit (TPU) (ADC) (DAC)
SD host
interface
(SDHI)
128-byte
RAM
MultiMediaCard 256-byte
interface (MMCIF) SRAM
Serial I/O
with FIFO
(SIOF0)
256-byte
SRAM
Serial I/O
with FIFO
(SIOF1)
SIM card
interface
(SIM)
PC card
controller
(PCC)
Figure 1.1 Block Diagram
1.3 Pin Assignments
1.3.1 Pin Assignments
Rev. 3.00 Jan. 18, 2008 Page 10 of 1458
REJ09B0033-0300