SH7720 Datasheet, PDF (410/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
This LSI
A14
A1
CKE
CKIO
CSn
64-Mbit SDRAM
(1M x 16 bits x 4 banks)
A13
A0
CKE
CLK
CS
RAS
CAS
RD/WR
D15
D0
DQMLU
DQMLL
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 9.13 Example of 16-Bit Data-Width SDRAM Connection
(2) Address Multiplexing
An address multiplexing is specified so that SDRAM can be connected without external
multiplexing circuitry according to the setting of bits BSZ[1:0]in CSnBCR, AxROW[1:0] and
AxCOL[1:0] in SDCR. Tables 9.12 to 9.17 show the relationship between the settings of bits
BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins. Do not specify
those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed.
A25 to A18 are not multiplexed and the original values of address are always output at these pins.
When the data bus width is 16 bits (BSZ[1:0] =B'10), A0 of SDRAM specifies a word address.
Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the
A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] =B'11), the A0 pin of
SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of
the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
Rev. 3.00 Jan. 18, 2008 Page 348 of 1458
REJ09B0033-0300