SH7720 Datasheet, PDF (668/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Bit Bit Name Initial Value R/W Description
0
DR
0
R/(W)* Receive Data Ready
Indicates that the receive FIFO data register
(SCFRDR) stores the data which is less than the
specified number of receive triggers, and that next
data is not yet received after 15 etu has elapsed
from the last stop bit in asynchronous mode.
0: Receive is in progress, or no received data
remains in SCFRDR after the receive ended
normally.
[Clearing conditions] (Initial value)
• Power-on reset, manual reset
• All receive data in SCFRDR is read, and DR is
read as 1, then written to with 0.
1: Next receive data is not received
[Setting condition]
SCFRDR stores the data which is less than the
specified number of receive triggers, and that next
data is not yet received after 15 etu has elapsed
from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the
8-bit 1-stop-bit format. (etu: Element
Time Unit)
Note: * The only value that can be written is 0 to clear the flag.
Rev. 3.00 Jan. 18, 2008 Page 606 of 1458
REJ09B0033-0300