SH7720 Datasheet, PDF (64/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 1 Overview
Table 1.1 SH7720/SH7721 Features
Item
CPU
DSP operating
unit
Features
• Renesas Technology Original SuperH architecture
• Upper compatibility with SH-1, SH-2, and SH3-DSP at object code level
• 32-bit internal data bus
• General-register
 Sixteen 32-bit general registers (eight 32-bit shadow registers)
 Five 32-bit control registers
 Four 32-bit system registers
• RISC type instruction set
 Instruction length: 16-bit fixed length for improved code efficiency
 Load/store architecture
 Delayed branch instruction
 Instruction set based on C language
• Instruction execution time: One instruction/cycle for basic instructions
• Logical address space: 4 Gbytes
• Space identifier ASID: 8 bits, 256 logical address spaces
• Five-stage pipeline
• Mixture of 16-bit and 32-bit instructions
• 32-/40-bit internal data bus
• Multiplier, ALU, barrel shifter, and DSP register
• 16-bit x 16-bit → 32-bit one cycle multiplier
• Large-capacity DSP data register file
 Six 32-bit data registers
 Two 40-bit data registers
• Extended Harvard architecture for DSP data buses
 Two data buses
 One instruction bus
• Up to four parallel operations: ALU, multiply, two loads, and store
• Two address units to generating addresses for two memory access
• DSP data addressing modes: Increment, index register addition (with or
without modulo addressing)
• Zero-overhead repeat loop control
• Conditional execution instructions
• User DSP mode and privileged DSP mode
Rev. 3.00 Jan. 18, 2008 Page 2 of 1458
REJ09B0033-0300