SH7720 Datasheet, PDF (1173/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 33 User Break Controller (UBC)
Section 33 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
33.1 Features
1. The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
• Address
Compares 40 bits configured of the ASID and addresses 32 bits: the ASID can be selected
either all-bit comparison or all-bit mask. Comparison bits are maskable in 1-bit units; user can
mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc.
One of the four address buses (logic address bus (LAB), internal address bus (IAB),
One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB)
and Y-memory data bus (YDB)) can be selected.
• Data
Only on channel B, 32-bit maskable.
One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB)
and Y-memory data bus (YDB)) can be selected.
• Bus cycle
Instruction fetch or data access
• Read/write
• Operand size
Byte, word, and longword
2. A user-designed user-break condition exception processing routine can be run.
3. In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
4. Maximum repeat times for the break condition (only for channel B): 2¹² – 1 times.
5. Eight pairs of branch source/destination buffers.
UBCS300S_000020020300
Rev. 3.00 Jan. 18, 2008 Page 1111 of 1458
REJ09B0033-0300