SH7720 Datasheet, PDF (872/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
Bit Bit Name Initial Value R/W Description
0
EP0i TS 0
R/W EP0i Transmit Complete
[Setting condition]
When data to be transmitted to the host is written to
EP0i, then data is normally transferred from the
function to the host, and an ACK handshake is
returned.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
25.3.2 Interrupt Flag Register 1 (IFR1)
IFR1 is an interrupt flag register for VBUS and EP3. When each flag is set to 1 and the interrupt is
enabled in the corresponding bit of IER1, an interrupt request is generated as specified by the
corresponding bit in ISR1. Clearing is performed by writing 0 to the bit to be cleared. Writing 1 is
not valid and nothing is changed.
Bit Bit Name
7 to 4 
3
VBUS MN
2
EP3 TR
Initial Value
All 0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value
should always be 0.
R USB Connection Status
Status bit to monitor the USBF_VBUS pin state.
Reflects the state of the USBF_VBUS pin.
0: Disconnected
1: Connected
R/W EP3 (Interrupt) Transfer Request
[Setting condition]
When an IN token is issued from the host to EP3 and
the FIFO buffer is empty.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
Rev. 3.00 Jan. 18, 2008 Page 810 of 1458
REJ09B0033-0300