SH7720 Datasheet, PDF (16/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

9.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 328
9.4.6 Refresh Timer Counter (RTCNT)......................................................................... 329
9.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 330
9.4.8 SDRAM Mode Registers 2, 3 (SDMR2 and SRMR3) ......................................... 330
9.5 Operation ........................................................................................................................... 331
9.5.1 Endian/Access Size and Data Alignment.............................................................. 331
9.5.2 Normal Space Interface ........................................................................................ 337
9.5.3 Access Wait Control ............................................................................................. 343
9.5.4 CSn Assert Period Expansion ............................................................................... 345
9.5.5 SDRAM Interface ................................................................................................. 346
9.5.6 Burst ROM (Clock Asynchronous) Interface ....................................................... 385
9.5.7 Byte-Selection SRAM Interface ........................................................................... 387
9.5.8 PCMCIA Interface................................................................................................ 392
9.5.9 Burst ROM (Clock Synchronous) Interface.......................................................... 400
9.5.10 Wait between Access Cycles ................................................................................ 401
9.5.11 Bus Arbitration ..................................................................................................... 401
9.6 Usage Notes ....................................................................................................................... 404
Section 10 Direct Memory Access Controller (DMAC)..................................... 407
10.1 Features.............................................................................................................................. 407
10.2 Input/Output Pins............................................................................................................... 409
10.3 Register Descriptions......................................................................................................... 410
10.3.1 DMA Source Address Registers (SAR_0 to SAR_5) ........................................... 411
10.3.2 DMA Destination Address Registers (DAR_0 to DAR_5) .................................. 412
10.3.3 DMA Transfer Count Registers (DMATCR_0 to DMATCR_5) ......................... 412
10.3.4 DMA Channel Control Registers (CHCR_0 to CHCR_5) ................................... 413
10.3.5 DMA Operation Register (DMAOR) ................................................................... 418
10.3.6 DMA Extended Resource Selectors 0 to 2 (DMARS0 to DMARS2)................... 420
10.4 Operation ........................................................................................................................... 424
10.4.1 DMA Transfer Flow ............................................................................................. 424
10.4.2 DMA Transfer Requests ....................................................................................... 426
10.4.3 Channel Priority.................................................................................................... 431
10.4.4 DMA Transfer Types............................................................................................ 434
10.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 444
10.5 Usage Notes ....................................................................................................................... 448
10.5.1 Notes on DACK Pin Output ................................................................................. 448
10.5.2 Notes on the Cases When DACK is Divided........................................................ 448
10.5.3 Other Notes........................................................................................................... 452
Rev. 3.00 Jan. 18, 2008 Page xvi of lxii