SH7720 Datasheet, PDF (677/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Table 18.3 Serial Transmit/Receive Formats
SCSMR Bits
CHR PE STOP
Serial Transmit/Receive Format and Frame Length
1 2345678 9
10 11 12
0 00
START
8-Bit data
STOP
0 01
START
8-Bit data
STOP STOP
0 10
START
8-Bit data
P STOP
0 11
START
8-Bit data
P STOP STOP
1 00
START
7-Bit data
STOP
1 01
START
7-Bit data
STOP STOP
1 10
START
7-Bit data
P STOP
1 11
START
7-Bit data
P STOP STOP
(2) Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the CKE bit in the
serial control register (SCSCR).
When an external clock is input at the SCK pin, the clock appropriate for the sampling rate should
be input. For example, when the sampling rate is 1/16, the clock frequency should be 8 times the
bit rate used.
(3) Transmitting and Receiving Data (SCIF Initialization)
Before transmitting or receiving, clear the TE and RE bits to 0 in SCSCR, then initialize the SCIF
as follows.
When changing the communication format, always clear the TE and RE bits to 0 before following
the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR).
Clearing TE and RE to 0, however, does not initialize the serial status register (SCSSR), transmit
FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their
previous contents.
Clear TE to 0 after all transmit data are transmitted and the TEND bit in the SCSSR is set. The
transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared
Rev. 3.00 Jan. 18, 2008 Page 615 of 1458
REJ09B0033-0300