SH7720 Datasheet, PDF (509/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
When an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external
device is accessed in word units, the DACK output is divided because of the data alignment. This
example is illustrated in figure 10.18.
CKIO
Address
CSn
RD
T1 T2 Taw T1 T2
Data
WEn
DACKn
(Active-low)
WAIT
Note: The DACK is asserted for the last transfer unit
of the DMA transfer. When the transfer unit is
divided into several bus cycles and the CSn is
negated between bus cycles, the DACK is also
divided.
Figure 10.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 3.00 Jan. 18, 2008 Page 447 of 1458
REJ09B0033-0300