SH7720 Datasheet, PDF (779/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
The number of channels in control data is specified by the CD0E and CD1E bits in SICDAR.
Table 21.8 shows the relationship between the number of channels in control data and bit settings.
Table 21.8 Setting Number of Channels in Control Data
Number of Channels
CD0E
1
1
2
1
Note: To use only one channel in control data, use channel 0.
Bit
CD1E
0
1
21.4.5 Control Data Interface
Control data performs control command output to the CODEC and status input from the CODEC.
The SIOF supports the following two control data interface methods.
• Control by slot position
• Control by secondary FS
Control data is valid only when data length is specified as 16 bits.
(1) Control by Slot Position (Master Mode 1, Slave Mode 1)
Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot
position of control data. This method can be used in both SIOF master and slave modes. Figure
21.7 shows an example of the control data interface timing by slot position control.
1 frame
SIOFSCK
SIOFSYNC
SIOFTxD
SIOFRxD
L-channel
data
Slot No.0
Control R-channel Control
channel 0
data
channel 1
Slot No.1 Slot No.2 Slot No.3
Specifications: TRMD[1:0]=00 or 10, REDG=0,
TDLE=1,
TDLA[3:0]=0000,
RDLE=1,
RDLA[3:0]=0000,
CD0E=1,
CD0A[3:0]=0001,
FL[3:0]=1110 (Frame length: 128 bits),
TDRE=1, TDRA[3:0]=0010,
RDRE=1, RDRA[3:0]=0010,
CD1E=1, CD1A[3:0]=0011
Figure 21.7 Control Data Interface (Slot Position)
Rev. 3.00 Jan. 18, 2008 Page 717 of 1458
REJ09B0033-0300