SH7720 Datasheet, PDF (963/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
Image for Display in
Memory
(X-Resolution × Y-
Resolution)
LCD Module
(X-Resolution × Number of Colors for
Y-Resolution) Display
Number of
Column
Address Bits of Burst Length of
SDRAM
LCDC (LDSMR*)
64 × 128
128 × 64
Monochrome 1 bpp
8 bits

9 bits

10 bits

2 bpp
8 bits

9 bits

10 bits

4 bpp
8 bits

(packed)
9 bits

10 bits

4 bpp
(unpacked)
8 bits
Not more than 16
bursts
9 bits

10 bits

6 bpp
8 bits
Not more than 16
bursts
9 bits

10 bits

Color
4 bpp
8 bits

(packed)
9 bits

10 bits

4 bpp
8 bits
Not more than 16
bursts
(unpacked) 9 bits

10 bits

8 bpp
8 bits
Not more than 16
bursts
9 bits

10 bits

Note: * Specify the data of the number of line specified as burst length that can be stored in
address of SDRAM same as that of ROW.
Rev. 3.00 Jan. 18, 2008 Page 901 of 1458
REJ09B0033-0300