SH7720 Datasheet, PDF (306/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Figure 8.1 shows a block diagram of the interrupt controller.
IRLQOUT
NMI
IRQ5 to IRQ0
IRL3 to IRL0
PINT5 to PINT0
DMAC
SCIF
SIOF
TMU
TPU
WDT
ADC
USBF
USBH
RTC
SIM
LCDC
PCC
MMC
I²C
CMT
AFEIF
SSL
SDHI
REF
6
4
Input/output
16
control
(Interrupt request)
Com-
parator
Priority
identifier
Interrupt
request
SR
I3 I2 I1 I0
CPU
PINTER
IPR
ICR
IRR0
Bus
interface
[Legend]
ICR: Interrupt control register
IPR: Interrupt priority register
IRR: Interrupt request register
PINTER: PINT interrupt enable register
REF: Refresh request in bus state controller
INTC
Figure 8.1 Block Diagram of INTC
Rev. 3.00 Jan. 18, 2008 Page 244 of 1458
REJ09B0033-0300