SH7720 Datasheet, PDF (158/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.7 DSP Mode Extended System Control Instructions
Instruction
STC RS, Rn
STC RE, Rn
STC.L RS, @-Rn
STC.L RE, @-Rn
LDC.L @Rn+, RS
LDC.L @Rn+, RE
LDC Rn,RS
LDC Rn, RE
Operation
RS→Rn
RE→Rn
Rn-4→Rn, RS→(Rn)
Rn-4→Rn, RE→(Rn)
(Rn)→RS, Rn+4→Rn
(Rn)→RE, Rn+4→Rn
Rn →RS
Rn→RE
Number of
Execution States
1
1
1
1
4
4
4
4
(3) Restrictions on Repeat Loop Control
(a) Repeat control instruction assignment
The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In
addition, note that at least one instruction is required between the SETRC instruction and a repeat
start instruction.
(b) Illegal instruction one or more instructions following the repeat detection instruction
If one of the following instructions is executed between an instruction following a repeat detection
instruction to a repeat end instruction, an illegal instruction exception occurs.
• Branch instructions
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE registers
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Note: This restriction applies to all instructions for a repeat loop consisting of one to three
instructions and to three instructions including a repeat end instruction.
Rev. 3.00 Jan. 18, 2008 Page 96 of 1458
REJ09B0033-0300