SH7720 Datasheet, PDF (800/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 Analog Front End Interface (AFEIF)
Bit
Bit Name
Initial Value R/W Description
1
TE
0
R/W Transmit Enable
0: Transmit operation is disabled. The READ
pointer of FIFO is stacked to the first address.
WRITE pointer is reset when 0 is written to this
bit. TFEM and THEM bits in ASTR1 is set to 1
at that time.
1: Transmit operation is enabled.
0
RE
0
R/W Receive Enable
0: Receive operation is disabled. The READ
/WRITE pointer is fixed to the first address.
Bits RFFM and RHFM in ASTR1 are set to 1 at
that time.
1: Receive operation is enabled
Table 22.2 FIFO Interrupt Size
Bit 4:
FFSZ2
0
Bit 3:
FFSZ1
0
1
1
0
1
Bit 2:
FFSZ0
0
1
0
1
0
1
0
1
FIFO Size
128
64
32
16
8
4
2
96
Description
TFE/RFF
THE/RHF
128 empty/full 64 empty/full
64 empty/full 32 empty/full
32 empty/full 16 empty/full
16 empty/full 8 empty/full
8 empty/full
4 empty/full
4 empty/full
2 empty/full
2 empty/full
1 empty/full
96 empty/full 48 empty/full
(Initial value)
Rev. 3.00 Jan. 18, 2008 Page 738 of 1458
REJ09B0033-0300