SH7720 Datasheet, PDF (936/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
Bit
9
8
7 to 0
Bit Name
AU1
AU0

Initial Value R/W
0
R/W
0
R/W
All 0
R
Description
Access Unit Select
Select access unit of VRAM. This bit is enabled when
ROT = 1 (rotate the display). When ROT = 0, 16-burst
memory read operation is carried out whatever the
AU setting is.
00: 4-burst
01: 8-burst
10: 16-burst
11: 32-burst
Notes: 1. Above burst lengths are used for 32-bit
bus. For 16-bit bus, the burst lengths are
twice the lengths of 32-bit bus.
2. When displaying a rotated image, the
burst length is limited depending on the
number of column address bits and bus
width of connected SDRAM. For details,
see tables 26.3 and 26.4.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 874 of 1458
REJ09B0033-0300