SH7720 Datasheet, PDF (830/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.3.1 Hc Revision Register (USBHR)
Bit
Bit Name
31 to 8 
7
Rev7
6
Rev6
5
Rev5
4
Rev4
3
Rev3
2
Rev2
1
Rev1
0
Rev0
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R Revision
0
R These read only bits include the BCD expression of the
0
R
HCI specification version implemented for the host
controller. The value H'10 corresponds to version 1.0. All
1
R
HCI implementation complying with this specification have
0
R ^{the value of H'10.}
0
R
0
R
0
R
24.3.2 Hc Control Register (USBHC)
The Hc Control register defines the operation mode for the host controller. The bits of this register
are amended only by the host controller driver (HCD) other than HCFS and RWC.
Bit
Bit Name
31 to 11 
10
RWE
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W Remote Wakeup Enable
This bit is set by HCD to enable/disable the remote
wakeup function at the same time as the detection of an
upstream resume signal.
This function is not supported. Be sure to write 0.
Rev. 3.00 Jan. 18, 2008 Page 768 of 1458
REJ09B0033-0300