SH7720 Datasheet, PDF (773/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.4.2 Serial Timing
(1) SIOFSYNC
The SIOFSYNC is a frame synchronous signal. Depending on the transfer mode, it has the
following two functions.
• Synchronous pulse: 1-bit-width pulse indicating the start of the frame
• L/R: 1/2-frame-width pulse indicating the left-channel stereo data (L) in high level and the
right-channel stereo data (R) in low level
Figure 21.3 shows the SIOFSYNC synchronization timing.
(a) Synchronous pulse
SIOFSCK
SIOFSYNC
SIOFTxD
SIOFRxD
(b) L/R
Start bit data
1-bit delay
SIOFSCK
SIOFSYNC
SIOFTxD
SIOFRxD
Start bit of left channel data
(1/2 frame length)
No delay
1 frame
1 frame
Start bit of right channel data
(1/2 frame length)
Figure 21.3 Serial Data Synchronization Timing
Rev. 3.00 Jan. 18, 2008 Page 711 of 1458
REJ09B0033-0300