SH7720 Datasheet, PDF (230/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Memory Management Unit (MMU)
4.1.1 MMU of This LSI
(1) Virtual Address Space
This LSI supports a 32-bit virtual address space that enables access to a 4-Gbyte address space. As
shown in figures 4.2 and 4.3, the virtual address space is divided into several areas. In privileged
mode, a 4-Gbyte space comprising areas P0 to P4 are accessible. In user mode, a 2-Gbyte space of
U0 area is accessible, and a 16-Mbyte space of Uxy area is also accessible if the DSP bit in the SR
register is set to 1. Access to any area (excluding the U0 area and Uxy area) in user mode will
result in an address error.
If the MMU is enabled by setting the AT bit in the MMUCR register to 1, P0, P3, and U0 areas
can be used as any physical address area in 1- or 4-kbyte page units. By using an 8-bit address
space identifier, P0, P2, and U0 areas can be increased to up to 256 areas. Mapping from virtual
address to 29-bit physical address can be achieved by the TLB.
(a) P0, P3, and U0 Areas
The P0, P3, and U0 areas can be address translated by the TLB and can be accessed through the
cache. If the MMU is enabled, these areas can be mapped to any physical address space in 1- or 4-
kbyte page units via the TLB. If the CE bit in the cache control register (CCR1) is set to 1 and if
the corresponding cache enable bit (C bit) of the TLB entry is set to 1, access via the cache is
enabled. If the MMU is disabled, replacing the upper three bits of an address in these areas with 0s
creates the address in the corresponding physical address space. If the CE bit in the CCR1 register
is set to 1, access via the cache is enabled. When the cache is used, either the copy-back or write-
through mode is selected for write access via the WT bit in CCR1.
If these areas are mapped to the on-chip module control register area or on-chip memory area in
area 1 in the physical address space via the TLB, the C bit of the corresponding page must be
cleared to 0.
(b) P1 Area
The P1 area can be accessed via the cache and cannot be address-translated by the TLB. Whether
the MMU is enabled or not, replacing the upper three bits of an address in these areas with 0s
creates the address in the corresponding physical address space. Use of the cache is determined by
the CE bit in the cache control register (CCR1). When the cache is used, either the copy-back or
write-through mode is selected for write access by the CB bit in the CCR1 register.
Rev. 3.00 Jan. 18, 2008 Page 168 of 1458
REJ09B0033-0300