SH7720 Datasheet, PDF (661/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
18.3.7 FIFO Error Count Register (SCFER)
SCFER is a 16-bit read-only register that indicates the number of receive data errors (framing
error/parity error).
Bit
15,14
13
12
11
10
9
8
7, 6
5
4
3
2
1
0
Bit Name Initial value R/W

All 0
R
PER5
0
R
PER4
0
R
PER3
0
R
PER2
0
R
PER1
0
R
PER0
0
R

All 0
R
FER5
0
R
FER4
0
R
FER3
0
R
FER2
0
R
FER1
0
R
FER0
0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Parity Error
Indicates the number of data, in which parity errors
are generated, in receive data stored in the receive
FIFO data register (SCFRDR) in asynchronous mode.
Bits 13 to 8 indicate the number of data with parity
errors after the ER bit in SCSSR is set.
If all 64-byte receive data in SCFRDR have parity
errors, bits PER5 to PER0 indicate 0s.
Reserved
These bits are always read as 0. The write value
should always be 0.
Framing Error
Indicates the number of data, in which framing errors
are generated, in receive data stored in the receive
FIFO data register (SCFRDR) in asynchronous mode.
Bits 5 to 0 indicate the number of data with framing
errors after the ER bit in SCSSR is set.
If all 64-byte receive data in SCFRDR have framing
errors, bits FER5 to FER0 indicate 0s.
Rev. 3.00 Jan. 18, 2008 Page 599 of 1458
REJ09B0033-0300