SH7720 Datasheet, PDF (798/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 Analog Front End Interface (AFEIF)
22.2 Input/Output Pins
Table 22.1 shows the pins for AFE interface.
Table 22.1 Pin Configuration
Pin Name
AFE_RDET
AFE_RLYCNT
AFE_SCLK
AFE_FS
AFE_RXIN
AFE_HC1
AFE_TXOUT
I/O
Input
Output
Input
Input
Input
Output
Output
Function
Ringing signal input
On-hook control signal
Shift clock
Frame synchronization signal
Serial receive data
AFE hardware control signal
Serial transmit data
22.3 Register Configuration
Registers for AFEIF are shown below. Byte access registers to these is inhibited.
• AFEIF control register 1 (ACTR1)
• AFEIF control register 2 (ACTR2)
• AFEIF status register 1 (ASTR1)
• AFEIF status register 2 (ASTR2)
• Make ratio count register (MRCR)
• Minimum pose count register (MPCR)
• Dial number queue (DPNQ)
• Ringing pulse counter (RCNT)
• AFE control data register (ACDR)
• AFE status data register (ASDR)
• Transmit data FIFO port (TDFP)
• Receive data FIFO port (RDFP)
Rev. 3.00 Jan. 18, 2008 Page 736 of 1458
REJ09B0033-0300