SH7720 Datasheet, PDF (249/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Memory Management Unit (MMU)
3. Do not use the same physical addresses for address translation information of different page
sizes.
The above restrictions apply only when performing accesses using the cache.
Note: When multiple items of address translation information use the same physical memory to
provide for future SuperH RISC engine family expansion, ensure that the VPN bits 20 to
10 are the same.
• When using a 4-kbyte page
Virtual address
31
13 12 11 10
0
VPN
Offset
Physical address
28
PPN
Virtual address 12 to 4
13 12 11 10
0
Offset
Cache
Physical address 28 to 10
• When using a 1-kbyte page
Virtual address
31
13 12 11 10
0
VPN
Offset
Physical address
28
PPN
Virtual address 12 to 4
13 12 11 10
0
Offset
Cache
Physical address 28 to 10
Figure 4.12 Synonym Problem (32-kbyte Cache)
Rev. 3.00 Jan. 18, 2008 Page 187 of 1458
REJ09B0033-0300