SH7720 Datasheet, PDF (854/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.3.22 Hc Rh Port Status 1 and Hc Rh Port Status 2 Registers (USBHRPS1, USBHRPS2)
USBHRPS 1 and USBHRPS 2 registers are used for base-controlling each port and to report the
port event. The lower word is used to reflect the port status while the upper word reflects the status
change. Some status bits have special writing (see below). If an attempt to write to a bit indicating
a change in port status occurs when a transaction in which a token is passed via a handshake is in
progress, the writing to the bit is delayed until the transaction is completed. Always write reserved
bits to 0.
Bit
Bit Name
31 to 21 
20
PRSC
19
OCIC
18
PSSC
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W Port Reset Status Change
This bit is set when the 10 ms port reset signal has
completed.
Writing a 1 clears this bit; writing a 0 has no effect.
0: Port reset is not complete
1: Port reset is complete
0
R/W Port Over Current Indicator Change
This bit is valid when an over-current condition is reported
on the base of each port. This bit is set when the root hub
changes the POCI bit. Writing a 1 clears this bit. Writing a
0 has no effect.
0: PortOverCurrentIndicator not changed
1: PortoverCurrentIndicator changed
0
R/W Port Suspend Status Change
This bit is set when all resume sequences have
completed. These sequences include 20 ms resume
pulse, LS EOP, and 3 ms resychronization delay. Writing a
1 clears this bit. Writing a 0 has no effect. This bit is
cleared also when the PRSC bit is set.
0: Port resume not completed
1: Port resume completed
Rev. 3.00 Jan. 18, 2008 Page 792 of 1458
REJ09B0033-0300