SH7720 Datasheet, PDF (138/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction
Instruction
Code
Operation
Privileged
Mode
Cycles T Bit
STC R7_BANK,Rn 0000nnnn11110010 R7_BANK→Rn
√
1
–
STC.L SR,@–Rn
0100nnnn00000011 Rn–4→Rn, SR→(Rn)
√
1
–
STC.L GBR,@–Rn
0100nnnn00010011 Rn–4→Rn, GBR→(Rn)
–
1
–
STC.L VBR,@–Rn
0100nnnn00100011 Rn–4→Rn, VBR→(Rn)
√
1
–
STC.L SSR,@–Rn
0100nnnn00110011 Rn–4→Rn, SSR→(Rn)
√
1
–
STC.L SPC,@–Rn
0100nnnn01000011 Rn–4→Rn, SPC→(Rn)
√
1
–
STC.L R0_BANK,@–Rn 0100nnnn10000011 Rn–4→Rn, R0_BANK→(Rn) √
1
–
STC.L R1_BANK,@–Rn 0100nnnn10010011 Rn–4→Rn, R1_BANK→(Rn) √
1
–
STC.L R2_BANK,@–Rn 0100nnnn10100011 Rn–4→Rn, R2_BANK→(Rn) √
1
–
STC.L R3_BANK,@–Rn 0100nnnn10110011 Rn–4→Rn, R3_BANK→(Rn) √
1
–
STC.L R4_BANK,@–Rn 0100nnnn11000011 Rn–4→Rn, R4_BANK→(Rn) √
1
–
STC.L R5_BANK,@–Rn 0100nnnn11010011 Rn–4→Rn, R5_BANK→(Rn) √
1
–
STC.L R6_BANK,@–Rn 0100nnnn11100011 Rn–4→Rn, R6_BANK→(Rn) √
1
–
STC.L R7_BANK,@–Rn 0100nnnn11110011 Rn–4→Rn, R7_BANK→(Rn) √
1
–
STS MACH,Rn
0000nnnn00001010 MACH→Rn
–
1
–
STS MACL,Rn
0000nnnn00011010 MACL→Rn
–
1
–
STS PR,Rn
0000nnnn00101010 PR→Rn
–
1
–
STS.L MACH,@–Rn 0100nnnn00000010 Rn–4→Rn, MACH→(Rn)
–
1
–
STS.L MACL,@–Rn 0100nnnn00010010 Rn–4→Rn, MACL→(Rn)
–
1
–
STS.L PR,@–Rn
0100nnnn00100010 Rn–4→Rn, PR→(Rn)
–
1
–
TRAPA #imm
11000011iiiiiiii
Unconditional trap exception –
occurs*²
8
–
Notes:
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased in the following conditions.
a. If there is a conflict between an instruction fetch and a data access
b. If the destination register of a load instruction (memory → register) is also used by
the following instruction.
For addressing modes with displacement (disp) as shown below, the assembler
description in this manual indicates the value before it is scaled (x 1, x 2, or x 4)
according to the operand size to clarify the LSI operation. For details on assembler
description, refer to the description rules in each assembler.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp:12 ; PC relative
Rev. 3.00 Jan. 18, 2008 Page 76 of 1458
REJ09B0033-0300