SH7720 Datasheet, PDF (696/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Start of simultaneous
transmission/reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR, and set transmit ₁
trigger number in TTRG1 and TTRG0
Set TFRST and RFRST bits in
SCFCR to 1
2
Clear TFRST and RFRST bits in
SCFCR to 0
Write transmit data to SCFTDR
3
Read TDFE and RDF bits in SCSSR
TDFE =1?
RDF =1?
No
Yes
Write 0 to TDFE and RDF bits in
SCSSR after reading 1 from them
1. Set the receive trigger number and
transmit trigger number in SCFCR.
2. Reset the receive FIFO and transmit
FIFO.
3. Write transmit data to SCFTDR, and
if there is receive data in the FIFO,
read receive data until there is less
than the receive trigger setting number,
read the TDFE and RDF bits in SCSSR,
and if 1, clear to 0.
4. Wait for one bit interval.
5. Transmission/reception is started when
the TE and RE bits in SCSCR are set
to 1. The TE and RE bits must be set
simultaneously.
6. After the end of transmission/reception,
clear the TE and RE bits to 0.
Wait
4
1-bit interval elapsed?
No
Yes
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data
interrupt, set TIE bit to 1
5
When using receive FIFO data
interrupt, set RIE bit to 1
TDFE =1?
RDF =1?
No
Yes
Read receive trigger number of
receive data bytes from SCFRDR
Clear TE and RE bits in SCSCR to 0 6
End of
transmission/reception
Figure 18.16 Sample Simultaneous Serial Transmission and Reception Flowchart (2)
(Second and Subsequent Transfer)
Rev. 3.00 Jan. 18, 2008 Page 634 of 1458
REJ09B0033-0300