SH7720 Datasheet, PDF (1176/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 33 User Break Controller (UBC)
33.2.2 Break Address Mask Register A (BAMRA)
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address
specified by BARA.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BAMA31 to All 0
BAMA 0
R/W Break Address Mask A
Specify bits masked in the channel A break address bits
specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
the break condition
1: Break address bit BAAn of channel A is masked and
is not included in the break condition
Note: n = 31 to 0
33.2.3 Break Bus Cycle Register A (BBRA)
BBRA is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2)
instruction fetch or data access, (3) read or write, and (4) operand size as the break conditions of
channel A.
Initial
Bit
Bit Name Value R/W Description
15 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CDA1
0
R/W L Bus Cycle/I Bus Cycle Select A
6
CDA0
0
R/W Select the L bus cycle or I bus cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Rev. 3.00 Jan. 18, 2008 Page 1114 of 1458
REJ09B0033-0300