SH7720 Datasheet, PDF (570/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
14.4 Interrupts
There is one source of TMU interrupts: underflow interrupts (TUNI).
14.4.1 Status Flag Set Timing
The UNF bit is set to 1 when TCNT underflows. Figure 14.6 shows the timing.
Pφ
TCNT
Underflow
signal
UNF
TUNI
H'00000000
(TCOR value)
Figure 14.6 UNF Set Timing
14.4.2 Status Flag Clear Timing
The status flag can be cleared by writing 0 from the CPU. Figure 14.7 shows the timing.
TCR write cycle
T1
T2
T3
Pφ
Peripheral address bus
UNF, ICPF
TCR address
Figure 14.7 Status Flag Clear Timing
Rev. 3.00 Jan. 18, 2008 Page 508 of 1458
REJ09B0033-0300