SH7720 Datasheet, PDF (708/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 20 I²C Bus Interface (IIC)
SCL
Output
control
Noise canceller
SDA
Output
control
Transmission/
reception
control circuit
ICDRT
ICDRS
Transfer clock
generation
circuit
ICCKS
ICCR1
ICCR2
ICMR
SAR
Noise canceller
ICDRR
Address
comparator
Bus state
decision circuit
Arbitration
decision circuit
ICEIR
ICSR
[Legend]
ICCR1: I²C bus control register 1
ICCR2: I²C bus control register 2
ICMR: I²C bus mode register
ICSR: I²C bus status register
ICIER: I²C bus interrupt enable register
ICDRT: I²C bus transmit data register
ICDRR: I²C bus receive data register
ICDRS: I²C bus shift register
SAR: Slave address register
ICCKS: I²C bus master transfer clock select register
Interrupt
generator
Figure 20.1 Block Diagram of I²C Bus Interface
Interrupt
request
Rev. 3.00 Jan. 18, 2008 Page 646 of 1458
REJ09B0033-0300