SH7720 Datasheet, PDF (562/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
Figure 14.1 shows a block diagram of the TMU.
Pφ
Prescaler
Bus interface
RTC output clock
TMU_SUNI
TUNI0
TUNI1
TUNI2
Clock
controller
Ch. 0
Counter
controller
Interrupt
controller
Ch. 1
Counter
controller
Interrupt
controller
Ch. 2
Counter
controller
Interrupt
controller
TSTR
TCR_0
TCNT_0
TCOR_0
TCR_1
TCNT_1
TCOR_1
TCR_2
TCNT_2
TCOR_2
[Legend]
TSTR: Timer start register
TCR: Timer control register
TCNT: Timer counter
TCOR:Timer constant register
TMU_SUNI, TUNI0, TUNI1, and TUNI2: Interrupt requests
Figure 14.1 Block Diagram of TMU
TMU
Rev. 3.00 Jan. 18, 2008 Page 500 of 1458
REJ09B0033-0300