SH7720 Datasheet, PDF (1008/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 27 A/D Converter
27.7 Usage Notes
27.7.1 Notes on A/D Conversion
(1) Notes on Clearing the ADF Bit in the ADCSR Register
Problem: Even though the ADCSR.ADF bit has been read as 1 and 0 was then written to the ADF
bit, the ADF bit has not been cleared to 0.
Condition: This problem arises when reading of the ADF bit coincides with setting of the bit to 1
upon the end of A/D conversion.
Avoiding the Problem: Follow any of procedures (a), (b), or (c) below.
(a) Ensure that setting of the ADF bit to 1 upon the end of A/D conversion does not coincide
with reading of the ADF bit. For example, read the ADF bit as 1 and then write 0 to the
bit during processing of the A/D conversion end interrupt (ADI) that is generated at the
end of A/D conversion (when the ADF is set to 1).
(b) If the ADF bit has not been cleared, repeat the operation of reading it as 1 and then
writing 0 to it.
(c) Initialize the ADC and clear the ADF bit by placing the ADC in the module standby state.
(2) Notes on A/D Conversion in Scan Mode
Problem: A/D conversion in scan mode is not stopped by clearing the ADCSR.ADST bit (to 0).
Condition: This problem arises when 0 is written to the ADST bit in ADCSR to stop A/D
conversion while A/D conversion in scan mode is in progress.
Avoiding the Problem: Place the ADC in module standby state after clearing the ADST bit (to 0).
Placing the ADC in the module standby state initializes the ADC and stops A/D conversion. When
further A/D conversion is required, restart A/D conversion after releasing the ADC from the
module standby state.
(3) Notes on Transferring the Result of A/D Conversion by the DMAC
Problem: An incorrect superfluous DMA transfer is included before DMA transfer of the correct
result of A/D conversion.
Rev. 3.00 Jan. 18, 2008 Page 946 of 1458
REJ09B0033-0300