SH7720 Datasheet, PDF (764/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
7
RFWM2 0
R/W Receive FIFO Watermark
6
RFWM1 0
5
RFWM0 0
R/W 000: Issue a transfer request when 1 stage or more of the
R/W
receive FIFO are valid.
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
the receive FIFO are valid.
101: Issue a transfer request when 8 or more stages of
the receive FIFO are valid.
110: Issue a transfer request when 12 or more stages of
the receive FIFO are valid.
111: Issue a transfer request when 16 stages of the
receive FIFO are valid.
• A transfer request to the receive FIFO is issued by the
RDREQ bit in SISTR.
• The receive FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
4
RFUA4 0
R
Receive FIFO Usable Area
3
RFUA3 0
2
RFUA2 0
R
Indicate the number of words that can be transferred by
R
the CPU or DMAC as B'00000 (empty) to B'10000 (full).
1
RFUA1 0
R
0
RFUA0 0
R
Rev. 3.00 Jan. 18, 2008 Page 702 of 1458
REJ09B0033-0300