SH7720 Datasheet, PDF (857/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
Initial
Bit
Bit Name Value R/W Description
4
PRS
0
R/W (Read) Port Reset Status
When this bit is set by writing to SetPortReset, the port
reset signal is output. This bit is cleared when PRSC is set
upon completion of a reset. When the CCS is cleared, this
bit is not set.
0: Port reset signal is not active
1: Port reset signal is active
(Write) Set Port Reset
Writing a 1 sets PortReset signal. Writing a 0 has no
effect. When the CCS bit is cleared, this write does not set
the PRS bit, instead, sets the CSC bit. This reports a reset
of the power disconnection port to the driver.
3
POCI
0
R/W (Read) Port Over Current Indicator
This bit is valid only when a root hub is placed in such a
way that an over-current condition is reported on the base
of each port. If the over-current report at each port is not
supported, this bit is cleared to 0. If this bit is cleared, all
power controls are normal in this port. If this bit is set, an
over-current status exists in this port. This bit always
reflects an over-current input signal.
0: No over-current condition
1: Over-current condition is detected
(Write) Clear Suspend Status
Writing a 1 initiates a resume. Writing a 0 has no effect. If
the PSS bit is set, a resume is initiated.
Rev. 3.00 Jan. 18, 2008 Page 795 of 1458
REJ09B0033-0300