SH7720 Datasheet, PDF (767/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
11
TDLA3 0
R/W Transmit Left-Channel Data Assigns 3 to 0
10
TDLA2 0
9
TDLA1 0
8
TDLA0 0
R/W Specify the position of left-channel data in a transmit
R/W ^{frame as B'0000 (0) to B'1110 (14).}
R/W ^{1111: Setting prohibited}
• Transmit data for the left channel is specified in the
SITDL bit in SITDR.
7
TDRE
0
R/W Transmit Right-Channel Data Enable
0: Disables right-channel data transmission
1: Enables right-channel data transmission
6
TLREP 0
R/W Transmit Left-Channel Repeat
0: Transmits data specified in the SITDR bit in SITDR
as right-channel data
1: Repeatedly transmits data specified in the SITDL bit
in SITDR as right-channel data
• This bit setting is valid when the TDRE bit is set to
1.
• When this bit is set to 1, the SITDR settings are
ignored.
5, 4

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
TDRA3 0
R/W Transmit Right-Channel Data Assigns 3 to 0
2
TDRA2 0
R/W Specify the position of right-channel data in a transmit
1
TDRA1 0
R/W ^{frame as B'0000 (0) to B'1110 (14).}
0
TDRA0 0
R/W ^{1111: Setting prohibited}
• Transmit data for the right channel is specified in
the SITDR bit in SITDR.
Rev. 3.00 Jan. 18, 2008 Page 705 of 1458
REJ09B0033-0300