SH7720 Datasheet, PDF (746/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
11
FL3
0
R/W Frame Length 3 to 0
10
FL2
0
R/W 00xx: Data length is 8 bits and frame length is 8 bits.
9
FL1
0
R/W 0100: Data length is 8 bits and frame length is 16 bits.
8
FL0
0
R/W 0101: Data length is 8 bits and frame length is 32 bits.
0110: Data length is 8 bits and frame length is 64 bits.
0111: Data length is 8 bits and frame length is 128 bits.
10xx: Data length is 16 bits and frame length is 16 bits.
1100: Data length is 16 bits and frame length is 32 bits.
1101: Data length is 16 bits and frame length is 64 bits.
1110: Data length is 16 bits and frame length is 128 bits.
1111: Data length is 16 bits and frame length is 256 bits.
Note: When data length is specified as 8 bits, control
data cannot be transmitted or received.
x: Don't care
7
TXDIZ
0
R/W SIOFTxD Pin Output when Transmission is Invalid*
0: High output (1 output) when invalid
1: High-impedance state when invalid
Note: Invalid means when disabled, and when a slot that
is not assigned as transmit data or control data is
being transmitted.
6
RCIM
0
R/W Receive Control Data Interrupt Mode
0: Sets the RCRDY bit in SISTR when the contents of
SIRCR change.
1: Sets the RCRDY bit in SISTR each time when the
SIRCR receives the control data.
5
SYNCAC 0
R/W SIOFSYNC Pin Polarity
Valid when the SIOFSYNC signal is output as
synchronous pulse in master mode.
0: Active-high
1: Active-low
Rev. 3.00 Jan. 18, 2008 Page 684 of 1458
REJ09B0033-0300