SH7720 Datasheet, PDF (369/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Bit
5 to 2
1
0
Initial
Bit Name Value R/W Description

All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
HW1
0
R/W Number of Delay Cycles from RD, WEn (BEn) negation to
HW0
0
R/W ^{Address, CSn negation}
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5BWCR
Initial
Bit
Bit Name Value R/W Description
31 to 21 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19

0
R Reserved
This bit is always read as 0. The write value should always
be 0.
Rev. 3.00 Jan. 18, 2008 Page 307 of 1458
REJ09B0033-0300