SH7720 Datasheet, PDF(1501/1524 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7720 Datasheet, PDF (1501/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Item

Table 35.6 Port F Data Register

(PFDR) Read/Write Operations

Page Revision (See Manual for Details)

1191 Changed

PFCR State

PFnMD1 PFnMD0 Pin State Read

0

1

Reserved ï£§

Write

ï£§

35.16 Port T

Figure 35.16 Port T

1211 Changed

Port T

PTT4 (input/output) / SCIF0_CTS (input) / TPUTO1 (output)

PTT3 (input/output) / SCIF0_RTS (output) / TPUTO0 (output)

PTT2 (input/output) / SCIF0_TxD (output) / IrTX (output)

PTT1 (input/output) / SCIF0_RxD (input) / IrRX (input)

PTT0 (input/output) / SCIF0_SCK (input/output)

Section 36 User Debugging

Interface (H-UDI)

36.3 Register Descriptions

36.3.3 Shift Register

36.3.4 Boundary Scan Register

(SDBSR)

1220 Added

ID register (SDID)

Shift register

1221 Added

Shift register is a 32-bit register. The upper 16-bits are

set in SDIR at Update-IR.

If shifted in, the shift-in value is shift out after the value

of the 32-bit shift register is shifted out.

1221 Changed

SDBSR is a 434-bit shift register, located on the PAD,

for controlling the â¦

Rev. 3.00 Jan. 18, 2008 Page 1439 of 1458

REJ09B0033-0300

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