SH7720 Datasheet, PDF (579/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 16-Bit Timer Pulse Unit (TPU)
Initial
Bit Bit Name Value R/W Description
15 to 8 
All 0 R
Reserved
These bits are always read as 0 and cannot be modified.
7
CCLR2 0
R/W Counter Clear 2, 1, and 0
6
CCLR1 0
R/W These bits select the TCNT counter clearing source.
5
CCLR0 0
R/W 000: TCNT clearing disabled
001: TCNT cleared by TGRA compare match
010: TCNT cleared by TGRB compare match
011: Reserved (setting prohibited)
100: TCNT clearing disabled
101: TCNT cleared by TGRC compare match
110: TCNT cleared by TGRD compare match
111: Reserved (setting prohibited)
4
CKEG1 0
R/W Clock Edge 1 and 0
3
CKEG0 0
R/W These bits select the input clock edge. When the input clock
is counted using both edges, the input clock period is halved
(e.g. φ/4 both edges = φ/2 rising edge). If phase counting
mode is used this setting is ignored.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges*
[Legend] X: Don't care
Note: * If Pφ/1 is selected for the input clock, operation is
disabled.
2
TPSC2 0
R/W Time Prescaler 2, 1, and 0
1
TPSC1 0
0
TPSC0 0
R/W These bits select the TCNT counter clock. The clock source
R/W ^{can be selected independently for each channel. Table 15.3}
shows the clock sources that can be set for each channel.
For more in formation on count clock selection, see table
15.4.
Rev. 3.00 Jan. 18, 2008 Page 517 of 1458
REJ09B0033-0300