SH7720 Datasheet, PDF (1178/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 33 User Break Controller (UBC)
33.2.4 Break Address Register B (BARB)
BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition
in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address
buses for break condition B.
Initial
Bit
Bit Name Value R/W Description
31 to 0 BAB31 to All 0
BAB0
R/W Break Address B
Stores an address which specifies a break condition in
channel B.
If the I bus or L bus is selected in BBRB, an IAB or LAB
address is set in BAB31 to BAB0.
If the X memory is selected in BBRB, the values in bits
15 to 1 in XAB are set in BAB31 to BAB17. In this case,
the values in BAB16 to BAB0 are arbitrary.
If the Y memory is selected in BBRB, the values in bits
15 to 1 in YAB are set in BAB15 to BAB1. In this case,
the values in BAB31 to BAB16 are arbitrary.
Table 33.1 Specifying Break Address Register
Bus Selection in
BBRB
L bus
I bus
X bus
Y bus
BAB31 to BAB17
XAB15 to XAB1
Don’t care
BAB16
BAB15 to BAB1
LAB31 to LAB0
IAB31 to IAB0
Don’t care
Don’t care
Don’t care
YAB15 to YAB1
BAB0
Don’t care
Don’t care
Rev. 3.00 Jan. 18, 2008 Page 1116 of 1458
REJ09B0033-0300