SH7720 Datasheet, PDF (253/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Memory Management Unit (MMU)
• Software (TLB Invalid Exception Handler) Operations
The software searches the page tables in external memory and assigns the required page table
entry. Upon retrieving the required page table entry, software must execute the following
operations:
A. Write the values of the physical page number (PPN) field and the values of the protection
key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of
the page table entry recorded in the external memory to the PTEL register.
B. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
C. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
D. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
RTE instruction should be issued after two instructions form the LDTLB instruction.
4.5.4 Initial Page Write Exception
An initial page write exception results in a write access when the virtual address and the address
array of the selected TLB entry are compared and a valid entry with the appropriate access rights
is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial
page write exception processing includes both hardware and software operations.
• Hardware Operations
In an initial page write exception, this hardware executes a set of prescribed operations, as
follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Exception code H'080 is written to the EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written to the SPC.
E. The contents of SR at the time of the exception are written to SSR.
F. The MD bit in SR is set to 1 to place the privileged mode.
G. The BL bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way that caused the exception is set in the RC field in MMUCR.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100 to invoke the user-written initial page write exception handler.
Rev. 3.00 Jan. 18, 2008 Page 191 of 1458
REJ09B0033-0300