SH7720 Datasheet, PDF (933/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
26.3.3 LCDC Data Format Register (LDDFR)
LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of
colors used for display so as to match the display driver software specifications.
Bit Bit Name Initial Value R/W
15 to 9 
All 0
R
8
PABD
0
R/W
7

0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Byte Data Pixel Alignment
Sets the pixel data alignment type in one byte of
data. The contents of aligned data per pixel are the
same regardless of this bit's setting. For example,
data H'05 should be expressed as B'0101 which is
the normal style handled by a MOV instruction of the
this CPU, and should not be selected between
B'0101 and B'1010.
0: Big endian for byte data
1: Little endian for byte data
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 871 of 1458
REJ09B0033-0300