SH7720 Datasheet, PDF (1184/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 33 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
13
SCMFDA 0
R/W I Bus Cycle Condition Match Flag A
When the I bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1 (not
cleared to 0). In order to clear this flag, write 0 into this
bit.
0: The I bus cycle condition for channel A does not
match
1: The I bus cycle condition for channel A matches
12
SCMFDB 0
R/W I Bus Cycle Condition Match Flag B
When the I bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel B does not
match
1: The I bus cycle condition for channel B matches
11
PCTE
0
R/W PC Trace Enable
0: Disables PC trace
1: Enables PC trace
10
PCBA
0
R/W PC Break Select A
Selects the break timing of the instruction fetch cycle
for channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
execution
1: PC break of channel A is set after instruction
execution
9, 8

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
DBEB
0
R/W Data Break Enable B
Selects whether or not the data bus condition is
included in the break condition of channel B.
0: No data bus condition is included in the condition of
channel B
1: The data bus condition is included in the condition
of channel B
Rev. 3.00 Jan. 18, 2008 Page 1122 of 1458
REJ09B0033-0300