SH7720 Datasheet, PDF (958/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
26.3.22 LCDC Memory Access Interval Number Register (LDLIRNR)
LDLIRNR controls the bus cycle interval when the LCDC reads VRAM. When LDLIRNR is set
to other than H′00, the LCDC does not access VRAM until the specified number of bus cycles
(accessing the external memory or on-chip registers) has been performed by the
CPU/DMAC/USBH. When LDLIRNR is set to H'00 (initial value), the LCDC accesses the
VRAM, the CPU/DMAC/USBH performs one bus cycle, and then the LCDC accessed VRAM.
CKIO
Bus cycle LCDC1 LCDC2 LCDC3 ^... LCDC16
CPU
CPU
...
CPU
LCDC1
...
16 bursts
(When displaying routated image,
4/8/16/32 can be selected.)
The number of bus cycles other than LCDC is set to
LIRN7 to LIRN0. (1 to 255 bus cycles)
Bit Bit Name
15 to 8 
7 to 0 LIRN7 to
LIRN0
Initial Value R/W
All 0
R
All 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
VRAM Read Bus Cycle Interval
Specifies the number of the CPU/DMAC/USBH
bus cycles which can be performed during burst
bus cycles to read VRAM by LCDC.
H'00: one bus cycle
H'01: one bus cycle
:
H'FF: 255 bus cycles
Rev. 3.00 Jan. 18, 2008 Page 896 of 1458
REJ09B0033-0300