SH7720 Datasheet, PDF (508/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CKIO
CPU
CPU
DMAC
1st acceptance
Non-sensitive period
2nd acceptance
Acceptance
started
Bus cycle
DREQ
(Overrun 1,
high-level)
DACK
(High-active)
CPU
CPU
1st acceptance
Non-sensitive period
DMAC
2nd acceptance
DMAC
3rd acceptance
Acceptance
started
Acceptance
started
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection
CKIO
Bus cycle
DREQ
DMAC
CPU
Last DMA transfer
DMAC
CPU
CPU
DACK
TEND
Figure 10.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection
Rev. 3.00 Jan. 18, 2008 Page 446 of 1458
REJ09B0033-0300