SH7720 Datasheet, PDF (842/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.3.9 Hc Control Head ED Register (USBHCHED)
USBHCHED includes a physical address of first ED in the control list.
Initial
Bit
Bit Name Value R/W Description
31 to 4 CHED27 to All 0
CHED0
R/W CHED
Physical address of first ED in the control list
3 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
24.3.10 Hc Control Current ED Register (USBHCCED)
USBHCCED register includes a physical address of current ED in the control list.
Initial
Bit
Bit Name Value R/W Description
31 to 4 CCED27 to All 0
CCED0
R/W CCED
Physical address of current ED in the control list
3 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
24.3.11 Hc Bulk Head ED Register (USBHBHED)
USBHBHED includes a physical address of first ED in the Bulk List.
Initial
Bit
Bit Name Value R/W Description
31 to 4 BHED27 to All 0
BHED0
R/W BHED
Physical address of first ED in the Bulk List
3 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 780 of 1458
REJ09B0033-0300