SH7720 Datasheet, PDF(737/1524 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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SH7720 Datasheet, PDF (737/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Section 20 I2C Bus Interface (IIC)

20.5 Interrupt Request

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,

NACK receive, STOP recognition, and arbitration lost/overrun error. Table 20.3 shows the

contents of each interrupt request.

Table 20.3 Interrupt Requests

Interrupt Request

Transmit Data Empty

Transmit End

Receive Data Full

STOP Recognition

NACK Receive

Arbitration Lost/Overrun Error

Abbreviation

TXI

TEI

RXI

STPI

NAKI

Interrupt Condition

(TDRE=1) â¢ (TIE=1)

(TEND=1) â¢ (TEIE=1)

(RDRF=1) â¢ (RIE=1)

(STOP=1) â¢ (STIE=1)

{(NACKF=1)+(AL=1)} â¢ (NAKIE=1)

When interrupt conditions described in table 20.3 are 1 and the I bit in CCR is 0, the CPU

executes an interrupt exception processing. Interrupt sources should be cleared in the exception

processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to

ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the

same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive

data of one byte may be transmitted.

Rev. 3.00 Jan. 18, 2008 Page 675 of 1458

REJ09B0033-0300

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