SH7720 Datasheet, PDF (583/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 16-Bit Timer Pulse Unit (TPU)
Initial
Bit Bit Name Value R/W Description
2
MD2
0
R/W Modes 2 to 0
1
MD1
0
R/W These bits are used to set the timer operating mode.
0
MD0
0
R/W 000: Normal operation
001: Reserved (setting prohibited)
010: PWM mode
011: Reserved (setting prohibited)
100: Phase counting mode 1
101: Phase counting mode 2
110: Phase counting mode 3
111: Phase counting mode 4
Note: * Operation when setting (BFWT, BFB, BFA) = (1, 1, 0) is the same as when setting
(BFWT, BFB, BFA) = (1, 0, 1). However, when the BFB bit is set to 1 (TGRB and TGRD
used together for buffer operation), the setting of (BFWT, BFB, BFA) = (1, 1, 1) should
be made. In this case, the value set in TGRA should also be set in TGRC because
TGRA and TGRC are also used together for buffer operation.
15.3.3 Timer I/O Control Registers (TIOR)
The TIOR registers are 16-bit registers that control the TPU_TO pin. The TPU has four TIOR
registers, one for each channel. The TIOR registers are initialized to H'0000 by a reset, but not
initialized in standby mode, sleep mode, or module standby.
TIOR register settings should be made only when TCNT operation is halted.
Care is required since TIOR is affected by the TMDR setting.
If the counting operation is halted, the initial value set by this register is output from the TPU_TO
pin.
Rev. 3.00 Jan. 18, 2008 Page 521 of 1458
REJ09B0033-0300