SH7720 Datasheet, PDF (1119/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
31.3.21 Interrupt Status Register 2 (INTSTR2)
The INTSTR2 controls the MMCIF interrupt output.
If setting condition is satisfied, FRDYI is set even though it has been cleared. Disable flag setting
by FRDYIE in INTCR2 before clearing FRDYI.
Initial
Bit
Bit Name Value R/W Description
7 to 2 
All 0

Reserved
These bits are always read as 0. The write value should
always be 0.
1
FRDY_TU 1
R
When FRDYI setting condition is satisfied.
Read value
0: When FIFO remained data is less than data set as
assert condition by DMACR
1: When FIFO remained data is other than data set as
assert condition by DMACR
0
FRDYIE 0
R/(W)* FIFO Preparation End Flag Enable
[Setting condition]
When FIFO remained data is less than data set as assert
condition by DMACR while FRDYIE = 1 and the DMAEN
bit is set.
[Clearing condition]
Write 0 after reading FRDYI = 1.
Note: * Cleared by writing 0 after reading 1.
Rev. 3.00 Jan. 18, 2008 Page 1057 of 1458
REJ09B0033-0300