SH7720 Datasheet, PDF (575/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 15.1 shows a block diagram of the TPU.
Section 15 16-Bit Timer Pulse Unit (TPU)
Pφ
Divider
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Clock
selection
Channel 0
Edge
selection
Counter
up
clear
Output
control
Note 1
TPU_TO0
TGRA
TGRB
TGRC
TGRD
Buffer
Comparator
TPU_TI2A
TPU_TI2B
TPU_TI3A
TPU_TI3B
Channel 1
Same as channel 0
TPU_TO1
Clock
selection
Edge
selection
Phase
comparison
Channel 2
TGRA
TGRB
TGRC
TGRD
Buffer
Comparator
Counter
up
down
clear
Output
control
Note 1
TPU_TO2
Note 1: Output disabled
Initial value
0, 1
Compare match
0, 1, toggle
Channel 3
Same as channel 2
Figure 15.1 Block Diagram of TPU
TPU_TO3
Rev. 3.00 Jan. 18, 2008 Page 513 of 1458
REJ09B0033-0300