SH7720 Datasheet, PDF (951/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
26.3.17 LCDC Power Management Mode Register (LDPMMR)
LDPMMR controls the power supply circuit that provides power to the LCD module. The usage
of two types of power-supply control pins, LCD_VCPWC and LCD_VEPWC, and turning on or
off the power supply function are selected.
Bit Bit Name Initial Value R/W Description
15
ONC3
0
R/W LCDC Power-On Sequence Period
14
ONC2
0
13
ONC1
0
12
ONC0
0
R/W Set the period from LCD_VEPWC assertion to
R/W ^{LCD_DON assertion in the power-on sequence of}
the LCD module in frame units.
R/W
Specify to the value of (the period) -1.
This period is the (c) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the
LCD Module. For details on setting this register,
see table 26.5, Available Power-Supply Control-
Sequence Periods at Typical Frame Rates. (The
setting method is common for ONA, ONB, OFFD,
OFFE, and OFFF.)
11
OFFD3
0
R/W LCDC Power-Off Sequence Period
10
OFFD2
0
9
OFFD1
0
8
OFFD0
0
R/W Set the period from LCD_DON negation to
R/W ^{LCD_VEPWC negation in the power-off sequence}
of the LCD module in frame units.
R/W
Specify to the value of (the period) -1.
This period is the (d) period in figures 26.4 to 26.7,
Power-Supply Control Sequence and States of the
LCD Module.
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
VCPE
0
R/W LCD_VCPWC Pin Enable
Sets whether or not to enable a power-supply
control sequence using the LCD_VCPWC pin.
0: Disabled: LCD_VCPWC pin is masked and fixed
low
1: Enabled: LCD_VCPWC pin output is asserted
and negated according to the power-on or
power-off sequence
Rev. 3.00 Jan. 18, 2008 Page 889 of 1458
REJ09B0033-0300