SH7720 Datasheet, PDF (284/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 Exception Handling
1. The contents of the SSR are restored into the SR to return to the processing state in effect
before the exception handling took place.
2. A delay slot instruction of the RTE instruction is executed.*²
3. Control is passed to the address stored in the SPC.
The above operations from 1 to 3 are executed in sequence. During these operations, no other
exceptions may be accepted. By changing the SPC and SSR before executing the RTE instruction,
a status different from that in effect before the exception handling can also be specified.
Notes: 1. The MMU registers are also modified if an MMU exception occurs.
2. For details on the CPU processing mode in which RTE delay slot instructions are
executed, please refer to section 7.5, Usage Notes.
7.2.2 Exception Vector Addresses
A vector address for general exceptions is determined by adding a vector offset to a vector base
address. The vector offset for general exceptions other than the TLB miss exception is
H'00000100. The vector offset for interrupts is H'00000600. The vector base address is loaded into
the vector base register (VBR) using the software. The vector base address should reside in the P1
or P2 fixed physical address space.
7.2.3 Exception Codes
The exception codes are written to bits 11 to 0 of the EXPEVT (for reset or general exceptions) or
the INTEVT and INTEVT2 (for interrupt requests) to identify each specific exception event. See
section 8, Interrupt Controller (INTC), for details of the exception codes for interrupt requests.
Table 7.1 lists exception codes for resets and general exceptions.
7.2.4 Exception Request and BL Bit (Multiple Exception Prevention)
The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1,
acceptance of general exceptions is restricted as described below, making it possible to effectively
prevent multiple exceptions from being accepted.
If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is
accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an
interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power
consumption mode.
Rev. 3.00 Jan. 18, 2008 Page 222 of 1458
REJ09B0033-0300