SH7720 Datasheet, PDF (325/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Bit
Bit Name Initial Value R/W Description
4
CMIR
0
R/W CMI Interrupt Request
Indicates whether the CMI (CMT) interrupt
request is generated.
0: CMI interrupt request is not generated
1: CMI interrupt request is generated
3

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
2
USBFI1R 0
R
USBFI1 Interrupt Request
Indicates whether the USBFI1 (USBF) interrupt
request is generated.
0: USBFI1interrupt request is not generated
1: USBFI1 interrupt request is generated
1
USBFI0R 0
R
USBFI0 Interrupt Request
Indicates whether the USBFI0 (USBF) interrupt
request is generated.
0: USBFI0 interrupt request is not generated
1: USBFI0 interrupt request is generated
0

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 263 of 1458
REJ09B0033-0300